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w681308 xxxx product description w681308 usb audio controller data sheet revision 1.2
w681308 xxxx product description table of content 1. general description ............................................................................................................................... ................ 6 2. features ............................................................................................................................... ........................................ 6 3. pin configuration ............................................................................................................................... ...................... 8 4. pin description ............................................................................................................................... ........................... 9 5. block diagram ............................................................................................................................... ........................... 11 6. memory map ............................................................................................................................... ................................ 12 6.1 p rogram m emory map ............................................................................................................................... ............ 12 6.2 d ata m emory map ............................................................................................................................... ................... 12 7. registers ............................................................................................................................... .................................... 13 7.1 mcu c lock r ate s elect r egister ....................................................................................................................... 13 7.2 i nterrupt c ontrol r egisters .............................................................................................................................. 1 3 7.3 k eypad io, lcd, uart and gpio c ontrol r egisters ......................................................................................... 13 7.4 g ain s tage and m ixer c ontrol r egisters ............................................................................................................ 14 7.5 pcm c ontrol r egisters ............................................................................................................................... ........ 14 7.6 codec c ontrol r egisters ............................................................................................................................... ... 14 7.7 spi c ontrol r egisters ............................................................................................................................... .......... 15 7.8 w2s c ontrol r egisters ............................................................................................................................... ........ 15 7.9 r ing t one (pwm) c ontrol r egisters .................................................................................................................. 16 7.10 f ull /h alf d uplex a coustic e cho c ancellation (aec) c ontrol r egisters ........................................................ 16 7.11 usb c ontroller r egisters ............................................................................................................................... ... 18 8. microcontroller ............................................................................................................................... .................... 21 8.1 f eatures ............................................................................................................................... ................................. 21 8.2 m emory o rganization ............................................................................................................................... ............ 21 8.2.1 program memory ............................................................................................................................... ................ 21 8.2.2 data memory ............................................................................................................................... ...................... 21 8.2.3 special function registers (sfr) ..................................................................................................................... 22 8.3 p ower m anagement ............................................................................................................................... ................ 22 8.4 r eset c onditions ............................................................................................................................... ................... 23 8.4.1 external reset ............................................................................................................................... .................... 23 8.4.2 watchdog reset ............................................................................................................................... ................. 23 8.5 i nterrupts ............................................................................................................................... .............................. 23 8.6 p rogramming t imers and c ounters ..................................................................................................................... 24 8.6.1 timers/counters 0 and 1 ............................................................................................................................... .... 24 8.6.2 timer/counter 2 ............................................................................................................................... .................. 25 2 rev1.2
w681308 xxxx product description 8.6.3 watchdog timer ............................................................................................................................... ................. 25 8.7 s erial p ort (uart) ............................................................................................................................... ................ 28 8.8 otp rom ............................................................................................................................... ............................... 28 9. clock control and reset ............................................................................................................................... .... 29 9.1 c lock c ontrol ............................................................................................................................... ....................... 29 9.1.1 overview ............................................................................................................................... ............................. 29 9.1.2 clock generation ............................................................................................................................... ................ 29 9.1.3 control register ............................................................................................................................... .................. 30 10. interrupt control ............................................................................................................................... ............. 31 10.1 o verview ............................................................................................................................... ................................ 31 10.2 f unctionality ............................................................................................................................... ......................... 31 10.3 i nterrupt c ontrol r egisters .............................................................................................................................. 3 2 11. interface logic ............................................................................................................................... .................... 33 11.1 s oftware k eypad s canner ............................................................................................................................... .... 33 11.2 gpio s ............................................................................................................................... .................................... 34 11.3 lcd c ontrol ............................................................................................................................... .......................... 35 11.4 uart i/o c ontrol ............................................................................................................................... .................. 35 12. pcm interface , gain stage and mixer ........................................................................................................ 36 12.1 pcm i nterface ............................................................................................................................... ....................... 36 12.2 g ain stage ............................................................................................................................... .............................. 36 12.3 m ixer ............................................................................................................................... ...................................... 37 12.4 c onnection c ase e xample ............................................................................................................................... ..... 37 12.5 m ixer c ase e xamples with r egister s etting ....................................................................................................... 39 12.6 i2s r egister s etting e xample .............................................................................................................................. 4 2 13. audio codec interface ............................................................................................................................... ...... 43 13.1 o verview ............................................................................................................................... ................................ 43 13.2 a udio codec s ignal p ath ............................................................................................................................... ..... 43 13.3 m icrophone i nterface and a uxiliary i nterface ................................................................................................... 44 14. serial peripheral interface .......................................................................................................................... 47 14.1 o verview ............................................................................................................................... ................................ 47 14.2 d ata and s ignal f ormat of spi ............................................................................................................................ 47 14.3 fsm of spi ............................................................................................................................... ............................. 47 14.4 fifo and ram of spi ............................................................................................................................... ............. 48 14.5 i nterrupt s ources ............................................................................................................................... ................. 48 15. nuvoton 2-wire serial bus .............................................................................................................................. 4 9 3 rev1.2
w681308 xxxx product description 15.1 o verview ............................................................................................................................... ................................ 49 16. ice function by jtag std. ieee 1149.1 ............................................................................................................ 49 16.1 o verview ............................................................................................................................... ................................ 49 16.2 s can c hains and jtag i nterface .......................................................................................................................... 49 16.3 p in d escription ............................................................................................................................... ...................... 49 16.4 r eset b ehavior ............................................................................................................................... ...................... 50 17. ring tone (pwm) generator ............................................................................................................................ 50 17.1 o verview ............................................................................................................................... ................................ 50 18. full/half duplex acoustic echo cancellation(aec) ............................................................................ 51 18.1 f unction c ontrol r egisters ............................................................................................................................... . 51 19. usb device controller and transceiver ................................................................................................. 52 19.1 o verview ............................................................................................................................... ................................ 52 19.2 f unctional d escription ............................................................................................................................... ......... 52 19.2.1 endpoints ............................................................................................................................... ....................... 53 19.2.2 descriptor ram ............................................................................................................................... .............. 54 20. electrical characteristics .......................................................................................................................... 55 20.1 a bsolute m aximum r atings ............................................................................................................................... .... 55 20.2 r ecommended o perating c onditions ................................................................................................................... 55 20.3 dc c haracteristics ............................................................................................................................... ............... 56 20.4 a nalog t ransmission c haracteristics ................................................................................................................. 56 20.5 a nalog d istortion and n oise p arameters ........................................................................................................... 57 20.5.1 8khz sampling ............................................................................................................................... ................ 57 20.5.2 16khz sampling ............................................................................................................................... .............. 57 20.5.3 48khz sampling ............................................................................................................................... .............. 58 20.6 p rogrammable o utput l inear r egulator ............................................................................................................ 58 20.7 usb phy e lectronic c haracteristics ( 25c, dvdd= 3.3v, vddl =1.8v) ......................................................... 59 20.8 usb pll e lectronic c haracteristics .................................................................................................................. 60 21. typical application reference circuit ..................................................................................................... 61 21.1 usb v o ip speaker phone application ................................................................................................................... 61 22. package dimensions ............................................................................................................................... ........... 62 23. ordering information ............................................................................................................................... ....... 63 24. revision history ............................................................................................................................... .................. 64 4 rev1.2
w681308 xxxx product description list of tables table 1 pin description ............................................................................................................................... ........................... 10 table 2 w681308 mcu sfr location ............................................................................................................................... ...... 22 table 3 interrupt priority structure ............................................................................................................................... ........... 23 table 4 timer mode/control tmod/tcon sfr .................................................................................................................... 24 table 5 timer 2 mode/control tmod/tcon sfr ................................................................................................................. 25 table 6 time-out values for watchdog timer ...................................................................................................................... 26 table 7 watchdog control wdcon sfr ............................................................................................................................... 26 table 8 watchdog control bits ............................................................................................................................... ................ 27 table 9 watchdog timer timeout control .............................................................................................................................. 2 7 table 10 serial control scon sfr ............................................................................................................................... ........ 28 table 11 jtag pin description ............................................................................................................................... ............... 49 table 12 w681308 usb endpoint definitions ........................................................................................................................ 53 table 13 usb descriptor ram definitions ............................................................................................................................. 54 list of figures figure 1 pin diagram ............................................................................................................................... ................................. 8 figure 2 w681308 function block diagram ........................................................................................................................... 11 figure 3 interrupt structure ............................................................................................................................... ..................... 31 figure 4 keypad scanning application circuit ........................................................................................................................ 33 figure 5 pcm interface, gain stage and mixer location ....................................................................................................... 36 figure 6 mixer connection case examples ........................................................................................................................... 37 figure 7 mixer examples with registers setting .................................................................................................................... 39 figure 8 w681308 codec signal path control .................................................................................................................... 43 figure 9 microphone voltage gain mode ............................................................................................................................... 45 figure 10 microphone current gain mode ............................................................................................................................. 45 figure 11 microphone auxiliary input mode ........................................................................................................................... 46 figure 12 spi block diagram ............................................................................................................................... .................. 47 figure 13 ring tone generator block ............................................................................................................................... ..... 50 figure 14 signal flow through acoustic echo cancellation in the speech processor .............................................................. 51 figure 15 usb function block diagram ............................................................................................................................... .. 52 figure 16 w681308 reference design application circuit ..................................................................................................... 61 5 rev1.2
w681308 xxxx product description 1. general description w681308 usb audio controller from nuvot on integrates fast 8051 microcontroller unit (mcu), universal serial bus (usb) 2.0 full speed compliant controller with phy, 16bit high quality analog to digital converter / digital to analog converter (adc/dac) with 8/16/48 khz wide band sampling rates, speaker phone and echo cancellation, 8 kb one time programmable (otp) program memory and 1 kb data memory in a single 48 pin low-profile quad flat package (lqfp). mcu includes joint test access group (jtag) in-circuit emulat ion(ice) interface and can handle customer programs such as keypad scan, lcd control, caller list download, and usb and codec control among other features. w681308 provides highest integration and low bom cost solution with 8051-based development platform for usb audio peripherals and usb voip devices such as skype? , ot her im and sip-based application. with nuvoton?s market proven codec product experience, w68130 8 is designed to provide high audio quality in voip and audio devices applications and deliver usb audio/voip solution with the shortest time to market, time to volume and time to profit 2. features 8 bit turbo mcu ? embedded 12/24/48 mhz turbo 8051 mcu with 4 clocks per machine cycle ? 1 kb system ram, 8 kb otp rom ? 256 byte internal ram (8051) ? power on reset circuit ? software idle mode ? in circuit emulation (ice ) through jtag interface ? high quality 16 bit mono audio linear codec ? built-in 8/16/48 khz sampling rate wideband mono audio codec and tr ue 16-bit resolution adc/dac with internal 24-bit audio processing for both record and playback ? analog microphone(mic) amplifier and speaker driver with internal programmable gain stage ? 82 db receive snr @ 8 ohm load usb 2.0 full speed (fs) interface with integrated phy ? usb 2.0 fs compliant device controller and phy with 12 mbps communication speed ? support 6 usb endpoints configuration: control, iso in/out, bulk in/out and interrupt in ? 512-byte ram-based usb descriptor for multiple usb device support through 8051 mcu ? less than 500ua supply current in suspend mode ? ? fully integrated cap-less micr ophone amplifier with microphone bias ? dual earphone / speaker driver and buzzer ? integrated dac switch for earphone or speaker phone integrated acoustic echo cancellation (aec) ? support both half-duplex aec and 32ms full duplex aec ? built-in digital auto gain control (agc) wi th microphone input for speaker phone application integrated keypad control pins and gpio ? suitable for voip application ? volume up and down ? dial / hang up ? microphone and speaker phone mute ? led indicators 6 rev1.2
w681308 xxxx product description ? number pad control ? user programmable keys ? keypad scanning ? lcd module interface control uart ? programmable uart port for serial data application pcm interface ? master linear pcm interface to external pcm device such as nuvoton?s prox codec/slic spi interface ? works in master mode to control liquid crystal di splay (lcd) module or other spi slave devices ? support winbond serial flash device with spi interface w2s 2 wire interface ? support 2 wire interface for eeprom three format page modes usb 5v voltage supply ? built-in linear regulator on chip supports 3.3v to 1.8v conversion for digital core power ? usb 5v to 3.3v supply power using external transistors package ? 48-pin lqfp package 7mmx7mmx1mm application ? usb audio peripheral box/ usb sound card ? usb microphone / usb mono headset ? wired and wireless usb voip phone with lcd ? usb voip ata and gateway ? pstn and usb voip dual phone ? general usb mcu and audio application 7 rev1.2
w681308 xxxx product description 3. pin configuration 43 42 41 40 39 38 37 48 47 46 45 44 regl 10 11 12 9 8 7 6 5 4 3 2 1 18 19 20 21 22 23 24 13 14 15 16 17 33 32 31 30 29 28 27 26 25 36 35 34 gpio3/led dvdd gpio0(tck) dgnd dp dn vddl gpio13/uartr(tms) dgnd xtali xtalo jtag gpio15/kx0 gpio24/ky4 gpio23/ky3 gpio22/ky2 gpio21/ky1 gpio1(tdi) gpio5/pcmt gpio4/pcmr gpio6/bclk gpio7/fs gpio12/csl gpio8/sdo gpio9/sdi gpio10/sclk gpio11/cs gpio2(tdo) vpp vref1 agnd mcp earp mco rgnd spp earn spn avdd vref2 agnd gpio14/uartt(ntrst) gpio20/ky0 gpio18/kx3 gpio17/kx2 gpio19/kx4 gpio16/kx1 w681308 48 pin lqfp figure 1 pin diagram 8 rev1.2
w681308 xxxx product description 4. pin description please refer to design guide for product design details. pin name pin no state in reset functionality pin type driver strength uartt /ntrst /gpio 14 1 pull-h uart tx data / jtag tap controller reset input /gpio 14 d i/o 2 ma uartr /tms /gpio 13 2 pull-h uart rx data / jtag tms input / gpio 13 d i/o 2 ma dgnd 3 digital ground supply voltage d p ? xtalo 4 crystal clock output a o ? xtali 5 crystal clock input a i ? vddl 6 logic supply voltage d p ? dvdd 7 digital supply voltage d p ? dn 8 usb d- connection a i/o ? dp 9 usb d+ connection a i/o ? dgnd 10 digital ground supply voltage d p ? led/gpio 3 11 pull-h led connection / gpio 3 d i/o 16 ma tck/gpio 0 12 pull-h jtag clock with internal pull up / gpio 0 d i/o 16 ma cs/gpio 11 13 pull-h chip select (used for spi flash or normal spi) /gpio 11 d i/o 2 ma sclk/gpio 10 14 pull-l serial port bit clock ( for spi flash or normal spi) /gpio 10 d i/o 2 ma sdi/gpio 9 15 pull-l serial port data in (spi flash/ spi) /gpio 9 d i/o 2 ma sdo/gpio 8 16 pull-h serial port data out (spi flash/ spi) /gpio 8 d i/o 2 ma csl/gpio 12 17 pull-h lcd, lcm chip select /gpio 12 d i/o 2 ma fs/gpio 7 18 pull-l pcm frame sync output /gpio 7 d i/o 2 ma bclk/gpio 6 19 pull-l pcm bit clock output or input / gpio 6 d i/o 2 ma pcmr/gpio 4 20 pull-l serial pcm receiv e data input / gpio 4 d i/o 2 ma pcmt/gpio 5 21 pull-l serial pcm transmit data output / gpio 5 d i/o 2 ma tdi/gpio 1 22 pull-h jtag data input / gpio 1 d i/o 2 ma 9 rev1.2
w681308 xxxx product description pin name pin no state in reset functionality driver pin type strength tdo/gpio 2 23 pull-l jtag data output / gpio 2 d i/o 2 ma vpp 24 reset signal for digital core . tie this pin to 6.75v for programming the otp rom a p ? agnd 25 analog ground supply voltage a p ? spn 26 speaker1 negative connection a o ? earn 27 speaker2 negative connection a o ? avdd 28 analog supply voltage a p ? earp 29 speaker2 positive connection a o ? spp 30 speaker1 positive connection a o ? agnd 31 analog ground supply voltage a p ? rgnd 32 low noise adc and dac reference a p ? mco 33 the microphone amplifier output a g ? mcp 34 microphone positive connection a o ? vref2 35 voltage reference a o ? vref1 36 voltage reference a o ? regl 37 linear regulator base control output a o ? ky4/gpio 24 38 pull-h keypad row y4 connection /gpio 24 d i/o 2 ma ky3/gpio 23 39 pull-h keypad row y3 connection /gpio 23 d i/o 2 ma ky2/gpio 22 40 pull-h keypad row y2 connection /gpio 22 d i/o 2 ma ky1/gpio 21 41 pull-h keypad row y1 connection /gpio 21 d i/o 2 ma ky0/gpio 20 42 pull-h keypad row y0 connection /gpio 20 d i/o 2 ma kx4/gpio 19 43 pull-l keypad column x4 connection /gpio 19 d i/o 2 ma kx3/gpio 18 44 pull-l keypad column x3 connection /gpio 18 d i/o 2 ma kx2/gpio 17 45 pull-l keypad column x2 connection /gpio 17 d i/o 2 ma kx1/gpio 16 46 pull-l keypad column x1 connection /gpio 16 d i/o 2 ma kx0/gpio 15 47 pull-l keypad column x0 connection /gpio 15 d i/o 2 ma jtag 48 pull-l tie to dgnd for normal operation. tie to dvdd to enable jtag function. d i 2 ma table 1 pin description note: all gpio pins modes are controlled by register settings. 10 rev1.2
w681308 xxxx product description 5. block diagram figure 2 w681308 function block diagram there are 4 major function block grou ps in the usb audio controller: ? turbo 8051 mcu, registers, otp/ra m memory and peripheral ports ? 16-bit audio quality codec with aec/agc ? usb 2.0 fs interface with sie, full speed phy and 6 end points ? spi / uart / i2c / pcm / i2s and gpio interfaces. 11 rev1.2
w681308 xxxx product description 6. memory map 6.1 program memory map memory is mapped into program memory and data memory. program memory is mapped from 0x0000 to 0x1fff (8 kb), it is used by internal otp. 6.2 data memory map size (byte) data memory address total available function 0x1440 ~ 0x1443 4 4 interrupt control registers 0x144a ~ 0x145f 22 20 keypad io, lcd, uart and gpio control registers 0x1460 ~ 0x146f 16 16 gain stage and mixer control registers 0x1470 ~ 0x1474 16 5 pcm control registers 0x1480 ~ 0x148a 16 11 codec control registers 0x14a0 ~ 0x14af 16 15 spi control registers 0x14b0 ~ 0x14ba 16 11 w2s control registers 0x14c0 ~ 0x14c5 16 5 ring tone(pwm) control registers 0x1600 ~ 0x167f 128 120 full/half duplex aec control registers 0x1680 ~ 0x16ff 128 16 agc control registers 0x1800 ~ 0x19ff 512 57 usb control registers 0x2000 ~ 0x23ff 1024 1024 usb ram based descriptor field 0x2800 ~ 0x2fff 2048 2048 full duplex aec ram 0x3000 ~ 0x33ff 1024 1024 system ram 12 rev1.2
w681308 xxxx product description 7. registers the registers are mapped by function. 7.1 mcu clock rate select register address name mode value at reset function 0x1440 mcu rate select r/w 0x00 mcu system clock rate selection 7.2 interrupt control registers address name mode value at reset function 0x1441 interrupt source r/w 0x00 enable / disable interrupt source 0x1442 interrupt enable r/w 0x00 enable / disable interrupt function 0x1443 interrupt priority r/w 0x00 set interrupt priority 7.3 keypad io, lcd, uart and gpio control registers address name mode value at reset function 0x144a~ 0x144b gpio [14:0] pull up/down control r/w 0x00 enable/disable gpio [14:0] pull up/down 0x144c~ 0x144f keypad i/o (gpio [24:15]) and gpio [14:0] pull up/down selection r/w 0x00 select pull up/down for keypad i/o (gpio [24:15]) and gpio [14:0] 0x1450~ 0x1453 keypad i/o(gpio [24:15]) and gpio [14:0] status r/w 0x00 indicate keypad i/o(gpio [24:15]) and gpio [14:0] pin status 0x1454~ 0x1457 keypad i/o(gpio [24:15]) and gpio [14:0 direction control r/w 0x00 select keypad i/o(gpio [24:15]) and gpio [14:0] input/output direction 0x1458~ 0x145b keypad i/o(gpio [24:15]) and gpio [14:0] interrupt control r/w 0x00 enable/disable keypad i/o(gpio [24:15]) and gpio [14:0] interrupt 0x145e lcd control r/w 0x00 enable/disable lcd data, clock and chip selection control. 0x145f uart i/o control r/w 0x00 enable /disable uart i/o control. 13 rev1.2
w681308 xxxx product description 7.4 gain stage and mixer control registers address name mode value at reset function 0x1460 gain stage and mixer control r/w 0x00 enable/disable gain stage for side tone gain, codec to aec gain, aec to codec gain, aec to mixer gain, mixer to aec gain and usb in/usb out gain. select mixer mode for usb, codec and pcm. 0x1461~ 0x1467 gain stage index r/w 0x00 set audio gain index register value (side tone gain, codec to aec gain, aec to codec gain, aec to mixer gain, mixer to aec gain, usb in and usb out gain) 0x1468~ 0x146b mcu record r 0x00 enable/disable mcu to monitor usb iso in/out data 0x146c~ 0x146f mcu play r/w 0x00 enable/disable mcu write data to usb and codec 7.5 pcm control registers address name mode value at reset function 0x1470 pcm control r/w 0x00 enable/disable pcm interface and bit clock / frame sync selection 0x1472 pcm frame sync length r/w 0x00 set frame sync pulse length 7.6 codec control registers address name mode value at reset function 0x1480 codec control r/w 0x00 enable/disable codec, select sampling rate and high pass frequency 0x1481 dither control r/w 0x00 e nable/disable dither function 0x1482~ 0x1483 codec adc digital gain r/w 0x04 0x00 set digital adc path gain 0x1484~ 0x1485 codec dac digital gain r/w 0x04 0x00 set digital dac path gain 0x1488 codec mic control r/w 0x00 set microphone bias voltage and bias resistor reference 0x1489 codec mic control r/w 0x00 select mic interface mode and set microphone gain 0x148a codec speaker control r/w 0x00 attenuate speaker phone/ earphone speaker and set speaker gain 0x148b codec analog control r/w 0x00 enable/disable codec analog block 14 rev1.2
w681308 xxxx product description 7.7 spi control registers address name mode value at reset function 0x14a0 spi clock and interface r/w 0x00 enable/disable spi interface and select spi bit clock rate 0x14a1 spi command interface control r/w 0x00 set spi interface command length, r/w and other control 0x14a2 spi data length rw 0x00 se t spi interface data field length 0x14a3 spi interrupt control r/w 0x00 enable/disable spi interface interrupt 0x14a4~ 0x14a8 spi command byte control rw 0x00 set spi interface command byte 1 to 5 0x14ab spi clock format control rw 0x00 set spi interface clock format 0x14ac spi fifo data rw 0x00 read/write data from spi interface fifo 0x14ad spi byte count r 0x00 current spi interface fifo counter value 0x14ae spi write count r/w 0x00 mcu current write point for spi interface fifo 0x14af spi read count r/w 0x00 mcu current read point for spi interface fifo 7.8 w2s control registers address name mode value at reset function 0x14b0 w2s enable r/w 0x00 enable /disable w2s bus controller 0x14b1 eeprom control r/w 0x00 set different page mode and page size of eeprom 0x14b2~ 0x14b3 w2s clock r/w 0x00 set w2s bit clock rate 0x14b4 w2s r/w fifo r/w 0x00 read /write w2s compatible device 0x14b5 w2s r/w operation control r/w 0x00 set w2s read/write and fifo control 0x14b6 w2s status r/w 0x00 indicate w2 s fifo space and ack signal status 0x14b7 fifo read pointer r/w 0x00 indicate w2s fifo read pointer 0x14b8 fifo write pointer r/w 0x00 indicate w2s fifo write pointer 0x14b9 ack failure detect r/w 0x00 set ack failure detect and indicate failure data pointer in fifo 0x14ba w2s miscellaneous control r/w 0x00 indicate status for scl_in, finite state machine state and interrupt signal status 15 rev1.2
w681308 xxxx product description 7.9 ring tone (pwm) control registers address name mode value at reset function 0x14c0 pwm clock r/w 0x00 enable/disable pwm operation clock 0x14c2 pwm tone1 control r/w 0x00 set tone 1 volume 0x14c3 pwm tone1 frequency r/w 0x00 set tone 1 frequency 0x14c4 pwm tone2 control r/w 0x00 set tone 2 volume 0x14c5 pwm tone2 frequency r/w 0x00 set tone 2 frequency 7.10 full/half duplex acoustic echo cancellation (aec) control registers address name mode value at reset function 0x1600 aec configuration r/w 0x96 se t aec configuration parameters 0x1601 aec reset control r/w 0x08 set aec power down and reset function 0x1602 aec mode control r/w 0x03 set aec fu ll/half duplex mode and noise suppressor 0x1605 double talk long term power time constant r/w 0x09 set time constant for long term power estimation of double talk 0x1606 double talk short term power time constant r/w 0x0b set time constant for short term power estimation of double talk 0x1607~ 0x1608 double talk hangover time r/w 0x0020 set hangover time window of double talk detection algorithm 0x1609~ 0x160a double talk deviation threshold r/w 0x19a8 set deviation power threshold of double talk 0x160b~ 0x161c double talk long term power threshold r/w 0x0000 set power threshold for lo ng term power estimation of double talk 0x160d~ 0x160e double talk short term power threshold r/w 0x1010 set power threshold for s hort term power estimation of double talk 0x160f aec divergence threshold r 0x0f set aec divergence threshold 0x1610 voice detect long term power time constant r/w 0x09 set time constant for long term power estimation of voice detect 0x1611 voice detect short term power time constant r/w 0x0b set time constant for short term power estimation of voice detect 0x1612~ 0x1613 voice detect hangover time r/w 0x0009 set hangover time window of voice detect detection algorithm 16 rev1.2
w681308 xxxx product description address name value at mode function reset 0x1614~ 0x1615 voice detect deviation threshold r/w 0x1998 set deviation power threshold of voice detect 0x1616~ 0x1617 voice detect long term power threshold r/w 0x1998 set power threshold for lo ng term power estimation of voice detect 0x1618~ 0x1619 voice detect short term power low threshold r/w 0x0ba8 set low power threshold for short term power estimation of voice detect 0x161a~ 0x161b voice detect short term power high threshold r/w 0x1038 set high power threshold for short term power estimation of voice detect 0x161c~ 0x161d voice detect short term power average threshold r/w 0x0000 set average power threshold for short term power estimation of voice detect 0x161e~ 0x161f power cut off control r/w 0x1998 set zero reference bias fo r power cut off estimation 0x1620~ 0x1621 agc threshold r/w 0x2000 set maximum output power of agc 0x1622~ 0x1623 agc noise threshold r/w 0x0320 set agc calculated input power with time constant 0x1624 agc gain from aec r/w 0x02 set maximum gain for post echo cancellation signal 0x1625 agc gain time constant r/w 0xbb set delay time constant for long term gain estimation 0x1626 agc gain time constant r/w 0x09 set delay time constant for short term gain estimation 0x1628 soft clip control r/w 0x00 enable/disable soft clip(sc) function 0x1629 soft clip normal gain index r/w 0x00 set gain index of voice detect for soft clip module at normal gain mode 0x162a soft clip low gain index r/w 0x00 set gain index of voice detect for soft clip module at low gain mode 0x162b~ 0x162c soft clip threshold r/w 0x1000 set threshold level to select soft clip gain mode 0x162d soft clip power time constant r/w 0x07 set time constant for short term power calculation of voice detect soft clip 0x162e soft clip gain time constant r/w 0x07 set time constant to smooth gain mode change of soft clip 0x1630 acoustic suppression 1 time constant r/w 0x77 set time constant of acoustic suppression (as1) for convergence towards target 0x1631- 0x1632 acoustic suppression 1 attenuation r/w 0x1ca8 set maximum attenuation value for acoustic suppression (as1) algorithm 0x1633 acoustic suppression 2 time constant r/w 0x77 set time constant of acoustic suppression (as2) for convergence towards target 0x1634~ 0x1635 acoustic suppression 2 attenuation r/w 0x1ca8 set maximum attenuation value for acoustic suppression (as2) algorithm 0x1638 noise suppressor control r/w 0xbb set noise suppressor gain index and short term power time constant 0x1639 noise suppressor gain time constant r/w 0xbb set time constant for rise and fall of noise suppressor gain index 17 rev1.2
w681308 xxxx product description address name value at mode function reset 0x163a~ 0x163b noise suppressor active power threshold r/w 0x03e8 set threshold level for active noise suppressor 0x1640~ 0x1641 short term power voice detector r 0x0000 indicate short term power calculated by the voice detector (vd). 0x1642~ 0x1643 long term power voice detector r 0x0000 indicate long term power calculated by the voice detector (vd). 0x1644~ 0x1645 voice detector power deviation r 0x0000 indicate power deviation estimated by the voice detector (vd). 0x1648~ 0x1649 short term power double talk r 0x0000 indicate short term power calculated by double-talk detector (dt). 0x164a~0x 164b long term power double talk r 0x0000 indicate long term power calculated by double-talk detector (dt). 0x164c~0x 164d double talk power deviation r 0x0000 indicate power deviation estimated by the double-talk detector (dt). 0x1680 agc control r/w 0x00 enable / disable agc and set max gain control 0x1681 agc initial gain control r/w 0x00 enable/disable agc initial gain setting 0x1682 agc gain time r/w 0x00 set decreasing and increasing gain time for agc 0x1683 agc peak release time r/w 0x00 set release time for agc peak voice level 0x1684 agc gain monitor r 0x00 indicate agc gain status 0x1685 agc gain region monitor r 0x00 indicate agc gain status at increasing, target or decreasing region. 0x1687~ 0x1689 agc short term power r 0x0000 indicate agc short term power estimation 0x168a~0x 168b agc target threshold r/w 0x0000 set agc target region threshold 0x168c~0x 168d agc noise low threshold r/w 0x0000 set agc noise low threshold level 0x168e~0x 168f agc noise high threshold r/w 0x0000 set agc noise high threshold level 7.11 usb controller registers address name mode value at reset function 0x1800 usb enable r/w 0x00 enable/ disable usb 1.1 function control 0x1801~ 0x1803 usb interrupt register a r/w 0x00 set usb endpoints interrupt enable, status and clear. 0x1804 ~ 0x1806 usb interrupt register b r/w 0x00 set usb endpoints interrupt enable, status and clear. 18 rev1.2
w681308 xxxx product description value at address name mode function reset 0x1807 ~ 0x1809 usb interrupt register c r/w 0x00 set usb audio class interrupt enable, status and clear. 0x1810 endpoint 0 ? control in/out r/w 0x00 set usb control in/out endpoint control 0x1811 control in data r/w 0x00 control in endpoint data. internal fifo has 1 byte for control in transmission. if the 3 rd token byte is not equal to 0x01 or 0x03 (hid set report application), this byte will be transmitted instead of control-in fifo and interrupt- in fifo content. 0x1828 ~ 0x182f control out data r 0x00 control out endpoint receiving data. 0x1830 endpoint 1 and 2 ? iso in/out r/w 0x00 set iso in/out endpoint control register. 0x1831 sampling frequency r 0x00 indicate iso sampling frequency 0x1832- 0x1833 record volume r 0x00 indicate current record volume 0x1834- 0x1835 play volume r 0x00 indicate current play volume 0x1836 hid control out information r 0x00 indicate first packet and valid length 0x1837 max volume r 0x00 indicate audio path max volume gain 0x1838 hid token information r/w 0x00 set hid token 3 rd byte 0x1839 hid descriptor length r/w 0x00 this register value must be equal to the usb descriptor with respect to the hid return length 0x1840 ~ 0x1847 iso sync speed r/w 0x00 set iso sync speed tuning parameter register. 0x1848 endpoint 3 ? bulk in control register r/w 0x00 set bulk in endpoint control register 0x1849 bulk in data w 0x00 set bulk in tr ansmission data register except final data. 0x184a bulk in final data w 0x00 set bulk in transmission final data register. 0x184b bulk in fifo empty flag r 0x00 indicate bulk in transmission data fifo empty flag. 0x1850 endpoint 4 ? bulk out control register r/w 0x00 set bulk out endpoint control register 19 rev1.2
w681308 xxxx product description value at address name mode function reset 0x1851 bulk out fifo length r 0x00 indicate bu lk out endpoint receiving data fifo length. 0x1852 bulk out data r 0x00 bulk out endpoint receiving data fifo. 0x1858 endpoint 5 ? interrupt in control register r/w 0x00 set interrupt in endpoint control register 0x1859 usb interrupt data length r/w 0x00 interrupt in endpoint transmission data length 0x1880 usb iso mcu enable r/w 0x00 enable iso in/out fifo access by mcu 0x1881 usb iso in fifo depth r 0x00 iso out fifo depth indication 0x1882 usb iso out fifo depth r 0x00 iso in fifo depth indication 0x1883~ 0x1884 usb iso in data r/w 0x00 iso in data sample will be written by mcu 0x1885~ 0x1886 usb iso out data r 0x00 iso in data sample will be read by mcu 0x2000- 0x21ff usb descriptor ram data filed r/w 0x00 usb descriptor 0x2200- 0x223f hid control-in data field r/w 0x00 hid control-in data field 0x2240- 0x227f hid interrupt-in data field r/w 0x00 hid interrupt-in data field 0x2300- 0x233f hid control-out data field r/w 0x00 hid control-out data field 20 rev1.2
w681308 xxxx product description 8. microcontroller 8.1 features ? 8-bit turbo 8051 microcontroller with 12/24/48 mhz speed ? 256 bytes of on chip internal data ram and 1k bytes external data ram ? instruction set compatible with nuvoton turbo 8051 ? three 8-bit i/o ports ? three 16-bit timers ? one full-duplex serial port ? on-chip debugger via jtag (joint test access group) port ? 7 interrupt sources with two level priorities ? programmable watchdog timer ? two 16-bit data pointers ? on chip 8 kb otp (one time programmable) memory 8.2 memory organization prog ram memory 8.2.1 8.2.2 on-chip 8k otp memory: all instructions are fetched for execution from this memory area. the movc instruction can also access this memory region. data memory the mcu can access 1k bytes of external data memory. this memory region is accessed by the movx instruction. additionally it has 256 bytes on chip ram which can be access ed either by direct addressing or by indirect addressing. some special function registers (sfrs) can only be accessed by direct addressing. direct&indirect addressing indirect ram addressing sfrs direct addressing only 1k byte ram 0 0 7 f f f 8 0 3 0 0 0 33 f f 8k byte opt internal rom 0 0 0 0 1 f f f 21 rev1.2
w681308 xxxx product description special function registers (sfr) 8.2.3 address byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 f8 eip f0 b e8 eie e0 acc d8 wdcon d0 psw c8 t2con t2mod rcap2l rcap2h tl2 th2 c0 pmr status ta b8 ip saden b0 p3 a8 ie saddr a0 p2 xramah 98 scon sbuf 90 p1 88 tcon tmod tl0 tl1 th0 th1 ckcon 80 p0 sp dpl dph dpl1 dph1 dps pcon table 2 w681308 mcu sfr location 8.3 power management the w681308 has idle mode operation features that ma nage and save power consumption of the device. enable idle mode the user can set the device into idle mode by writing 1 to the pcon bit of sfr. the instruction t hat sets the idle bit is the l ast instruction that will be executed before the device goes into idle mode. in the id le mode, the clock to the mcu is halted but not to the interrupt, timer, watchdog timer, and serial ports blocks. this forces the mcu st ate to be frozen; the program counter, the stack pointer, t he program status word, the accumulator and the other registers hold t heir contents. the ale and psen pins are held high during the idle state. the port pins hold the logical states they had at the time idle was activated. the idle mode can be terminated in two ways: ? activation of any enabled interrupt since the interrupt controller is still acti ve, the activation of any enabled interrupt can wake up the processor. this will automatically clear the idle bit, terminate the idle mode, and the interrupt service routine (isr) will be executed. after the isr, execution of the program will continue from the instruction which put the device into idle mode. 22 rev1.2
w681308 xxxx product description ? activation of reset the idle mode can also be exited by activating the reset. the device can be put into reset either by applying a high on the external rst pin, a power on reset condition or a watchdog time r reset. the external reset pin has to be held high for at least two machine cycles i.e. 8 clock periods to be recognized as a valid reset. in the reset condition the program counter is reset to 0000h and all the sfrs are set to the reset condition. since the clock is already running there is no delay and execution starts immediately. in idle mode, the watchdog timer continues to run, and if enabled, a time-out will cause a watchdog timer interrupt which will wake up the device. the soft ware must reset the watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-ou t. when the w681308 is exiting from an idle mode with a reset, the instruction following the one which put the device into idle mode is not execut ed. so there is no danger of unexpected writes. 8.4 reset conditions there are two ways to put device into re set state: external reset and watchdog reset. 8.4.1 8.4 exte rnal reset the device continuously samples the rst pin at state c4 of every machine cycle. t herefore the rst pin must be held for at least 2 machine cycles to ensure detection of a valid rst high. the reset circuitry then synchronously applies the internal reset signal. thus the reset is synchronous operation and requir es the clock to be running to cause an external reset. once the device is in reset condition, it will remain so long as rs t is 1. even after rst is deactivated, the device will continue t o be in reset state for up to two machine cycles , and then begin program execution from 0000h. .2 wa tchdog reset the watchdog timer is a free-running timer with programmable time -out intervals. the user can clear the watchdog timer at any time, causing it to restart the count. when the time-out interval is reached an interrupt flag is set. if the watchdog rese t is enabled and the watchdog timer is not cl eared, then 512 clocks from the flag bein g set, the watchdog timer will generate a reset. this places the device into the reset condition. the rese t condition is maintained by hardware for two machine cycles. once the reset is removed the device will begin execution from 0000h. 8.5 interrupts the w681308 mcu has three priority levels interrupt structure with 7 interrupt sources. each of the interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. additionally, all the interrupts can be globally enabled or dis abled. source flag priority vector address external interrupt 0 ie0 1 (highest) 0003h timer 0 overflow tf0 2 000bh external interrupt 1 ie1 3 0013h timer 1 overflow tf1 4 001bh serial port ri + ti 5 0023h timer 2 overflow tf2 + exf2 6 002bh watchdog timer wdif 7 (lowest) 0063h table 3 interrupt priority structure 23 rev1.2
w681308 xxxx product description 8.6 programming timers and counters the mcu of w681308 has three 16-bit programmable ti mers/counters and one programmable watchdog timer. the watchdog timer is operationally quite diffe rent from the other three timers. timers/counters 0 and 1 8.6.1 timer 0 (tm0) and timer 1 (tm1) are 16-bit timer/counters and ar e nearly identical. each of these timers/counters has two 8 bit registers which form the 16 bit counting register. for time r/counter 0 they are th0, the upper 8 bits register, and tl0, the lower 8 bit register. similarly timer/counter 1 has two 8 bi t registers, th1 and tl1. the tw o timers can be configured to operate either as timers to count machine cycl es or as counters counting external inputs. in timer mode, the timer counts clock cycles. the timer clo ck can be programmed to be thought of as 1/12 of the system clock or 1/4 of the system clock. in counter mode, the register is incremented on the falling edge of the corresponding external input pins, t0 for timer 0 and t1 for timer 1. the t0 and t1 inputs are sampled in every machine cycle at c4. if the sampled value is high in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized and the c ount register is incremented. since it takes two machine cycles to recognize a negative tr ansition on the pin, the minimum period at which counting will take place is double of the machine cycle. in either the timer or counter mode, the count regist er will be updated at c3. therefore, in the time r mode, the recognized negative transition on pin t0 and t1 can caus e the count register value to be updated only in the machine cycle following the one in which the negative edge was detected. the timer or counter function is selected by the c/t bit in the tmod special function register. each timer/counter has one selection bit for its own. bit 2 of tm od selects the function for timer/counter 0 and bit 6 of tmod selects the function for timer/counter 1. 89h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmod gate c/t m1 m0 gate c/t m1 m0 88h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 table 4 timer mode/control tmod/tcon sfr 24 rev1.2
w681308 xxxx product description 8.6 .2 ti mer/counter 2 timer/counter 2 is a 16 bit up/down counter which is conf igured by the t2mod register and controlled by the t2con register. timer/counter 2 is equipped with a capture/reload capability. as with the timer 0 and timer 1 counters, they provide wide selection and control of the clock and selection of the operating modes. the clock source for timer/ counter 2 can be selected for the crystal oscillator, which is divided by 12 or 4 ( c/t2 = 0). the clock is then enabled when tr2 is a 1, and disabled when tr2 is a 0. c9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t2mod - - - - t2cr - - dcen t2con tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 table 5 timer 2 mode/control tmod/tcon sfr 8.6 .3 wa tchdog timer the watchdog timer is a free-running timer that can be programm ed by the user to serve as a system supervisor, a time- base generator or an event timer. it is basic ally a set of dividers that divide the system clock. the divider output is selecta ble and determines the time-out interval. when the time-out occurs t he flag wdif is set, which can cause an interrupt if enabled, and a system reset can also be caused if it is enabled. the interrupt will occur if the individual interrupt enable and the glo bal enable are set. the interrupt and reset functions are indepen dent of each other and may be used separately or together depending on the software employed. 24 25 26 27 23 22 0 wd1 , wd 0 time-out wdif wtrf 512 clock delay ewd(eie.4 ) interru pt res et enable watchdog timer reset ewt(wdcon.1) 00 01 10 11 reset watchdog pwt(wdcon. fosc 12/24/ 48mhz when used as a simple timer, the reset and interrupt functions are disabled. the timer will set the wdif flag each time the timer completes the selected time interv al. the wdif flag is polled to detect a time-out and the rwt allows software to restart the timer. the watchdog timer can also be used as a very long timer. the interrupt feature is enabled in this case. every time the time-out occurs an interrupt wi ll occur if the global interrupt enable ea is set. 25 rev1.2
w681308 xxxx product description the main use of the watchdog timer is as a system monitor. this is important in r eal-time control applications. in case of some power glitches or electro-magnetic interference, the processor may begin to execute errant code. if this is left unchecked the entire system may crash. using the watchdog timer interrupt during software development will allow the user to select ideal watchdog reset locations. the code is first written without the watchdog interrupt or reset. then the watchdog interrupt is enabled to identify code locations where interrupt occurs. the user can now insert instructions to reset the watchdog timer which will allow the code to run without any watchdog timer interrupts. now the watchdog timer reset is enabled and the watchdog interrupt may be disabled. if any err ant code is executed now, then the reset watchdog timer instructions will not be execut ed at the required instants and watchdog reset will occur. wd1 wd0 watchdog interval number of clocks time@12mhz time@24mhz time@48mhz 0 0 2 23 8388608 699.05 ms 349.53 ms 174.76 ms 0 1 2 25 33554462 2796.20 ms 1398.10 ms 699.05 ms 1 0 2 26 67108864 5592.41 ms 2796.20 ms 1398.10 ms 1 1 2 28 268435456 22369.62 ms 11184.81 ms 5592.41 ms table 6 time-out values for watchdog timer the watchdog timer will be disabled by a power-on/fail reset. the watchdog timer reset does not disable the watchdog timer, but will restart it. note: in general, software should restart the timer to put it into a known state. d8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdcon - por - - wdif wtrf ewt rwt external reset 0 x 0 x 0 x x 0 table 7 watchdog control wdcon sfr control bit name function por power-on reset flag hardware will set this flag on a power up condition. this flag can be read or written by software. a write by software is the only way to clear this bit once it is set. wdif watchdog timer interrupt flag this bit is set by hardware to indicate that the time-out period has elapsed and invoke watch dog timer interrupt if enabled(ewdi=1). this bit must be cleared by software. wtrf watchdog timer reset flag hardware will set this bit when the watchdog timer causes a reset. software can read it but must clear it manually. a power-fail reset will also clear the bit. this bit helps software in determining the cause of a reset. if ewt = 0, the watchdog timer will have no affect on this bit. 26 rev1.2
w681308 xxxx product description control bit name function ewt enable watchdog timer reset setting this bit will enable the watchdog timer reset function. rwt reset watchdog timer this bit helps in putting the watchdog time r into a know state. it also helps in resetting the watchdog timer before a time-o ut occurs. failing to set the ewt before time-out will cause an interrupt, if ewdi (eie.4) is set, and 512 clocks after that a watchdog timer reset will be generated if ewt is set. this bit is self-clearing. table 8 watchdog control bits wtrf is set to a 1 on a watchdog timer reset, set to 0 on power on/down resets. wtrf is not altered by an external reset. por is set to 1 by a power-on reset. ewt is cleared to 0 on a power-on reset and unaffected by other resets. to prevent software from accidentally enabling or disabling the watch dog reset function, t he bit of wdcon requires time access (ta) procedure to write. example: mov ta, #0aah mov ta, #055h clr wdif wd1, wd0 are time-out bits for watchdog timer located at ckcon.7 and ckcon.6. these bits determine the time-out period of the watchdog timer. the reset time-out per iod is 512 clocks longer than the watchdog time-out. wd1 wd0 interrupt time-out reset time-out 0 0 2 23 2 23 + 512 0 1 2 25 2 25 + 512 1 0 2 26 2 26 + 512 1 1 2 28 2 28 + 512 table 9 watchdog timer timeout control 27 rev1.2
w681308 xxxx product description 8.7 serial port (uart) the mcu serial port is a full-duplex port, and the mcu provid es additional features, such as frame error detection and automatic address recognition. the serial port is capable of synchronous and asynchronous communication. in synchronous mode, the mcu generates the cl ock and operates in half-duplex mode. in asynchronous mode, the serial port can simultaneously transmit and receive data. the transmit regi ster and the receive buffer are both addressed as sbuf, but any write to sbuf writes to the transmit register while any r ead from sbuf reads from the receive buffer. the serial port can operate in four modes: mod 0, mod 1, mod 2 and mod 3. 98h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scon sm0/fe sm1 sm2 ren tb8 rb8 ti ri table 10 serial control scon sfr 8.8 otp rom the w681308 internal otp rom is designed to store all application firmware. ? 8kb one-time programmable logic device the otp programming is done by the injecti on of hot electrons which are generated by avalanche impact ionization in the bit cell. user can enter jtag mode to program 8k otp rom throug h jtag interface pins and signal of pcmt pin will go high simultaneously. the signal of pin pcmt can be used to c ontrol external hardware device to apply 6.75v or 3.3v to programming voltage pin vpp. the cells are initialized by ultr aviolet light through internal photoemission from the floating gate. ? enable otp read protection you can write zero to bit 7 of otp address 0x1fff to turn on the read protection feature. 28 rev1.2
w681308 xxxx product description 9. clock control and reset 9.1 clock control over view 9.1.1 9.1.2 each register in the 12/24/48 mhz usb audio controller is reset synchronously. the reset and clock control function ensures that the system reset signal is correctly generated. the system reset signal is also used to ensure that bi-directional signals are all set to input during initialization. cloc k generation the crystal oscillator circuit and the external attachment of a 12 mhz quartz crystal or ceramic resonator is shown below. the rf is used to dc bias the internal am plifier to operate in the linear region. the r1, c1, and c2 are chosen so as not to overdrive the crystal and to suppress osc illation at higher harmonics. rf = 1m ? , r1=270 ? , c1 and c2 are to be 33pf each. xtal_in c1 c2 xtal_out external crystal rf r1 the pll block diagram is shown below. the pll uses the output of the crystal oscillator as its reference clock and generate a 48 mhz clock. 29 rev1.2
w681308 xxxx product description cont rol register 9.1.3 mcu rate select address access mode value at reset 0x1440 r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcu rate select [7:6] reserved reserved reserved reserved reserved reserved mcu rate select [7:6] mcu clock rate select (default = 00 ) 00 = 12 mhz , use for codec/aec/usb controller 01 = 24 mhz 10 = 48 mhz , use for mcu/usb phy/peripherals 11 = reserved 30 rev1.2
w681308 xxxx product description 10. interrupt control 10.1 overview the w681308 generates internal events, these interrupt events are triggered by the interrupt control logic. the mcu supports two priority levels of interrupts with 6 interrupt sources. 10.2 functionality the external interrupts int0 and int1 can be either edge triggered or level triggered, the interface and support logic gener ate the following interrupts: ? nfs interrupt ? keypad-wakeup interrupt ? gpio interrupt ? spi interrupt ? w2s interrupt ? usb interrupt three registers control t he generation of interrupts in the w 681308, the interrupt source regi ster, the interrupt enable regist er and the interrupt priority register. each interrupt has a corresponding bit in these three registers. the interrupt source register is set when an interrupt event occurs and is cleared by mcu. when the mcu writes to interrupt source, any bit that is set to 1 cause the corresponding bit of interrupt source to be cleared , bits set to 0 are not affected (write ?one? to clear). an interrupt is generated when (interrupt s ource) & (interrupt enable) =1 for any of the interrupt sources. for each bit; if interrupt priority = 0, the interrupt is issued to int0, if interrupt priority = 1, the interrupt is issued to int1. figure 3 interrupt structure int0 int1 interrupt priority interrupt enable interrupt source & & & 31 rev1.2
w681308 xxxx product description 1 0.3 interrupt control registers address access mode value at reset 0x1441 ~ 0x1443 r/w 0x00 address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x1441 usb interrupt w2s interrupt spi interrupt gpio interrupt keypad- wakeup interrupt nfs interrupt reserved reserved note: the nfs interrupt occurs for every 8 codec frames. interrupt source register (0x1441) read: 1 = interrupt 0 = no interrupt write: 1 = clear interrupt enable register (0x1442) 1 = enable 0 = disable interrupt priority register (0x1443) 0 = int0 1 = int1 32 rev1.2
w681308 xxxx product description 11. interface logic the w6 erface log ? interface n ? interf ? jtag interf ? nte ? spi for serial data flash vered in this section. 11.1 ne the keypads consist of a number of b ted in a row/column arrangement as shown in figur 81308 int ic consists of: keypad scanner input/output gpio ports ? ? lcd/lcm i uart terface ace ace pcm i rface ? w2s interface keypad scanner, gpio, lcd/lcm and uart in terfaces are co soft pad scan ware key r uttons, connec e 4 the default pin kx[4: 0] is pin ky[4:0] is pull-h, user can foll ow below steps to scan the keypad by ware: 1. program kx[4:0] pin to output direction and output data 0. program ky[4:0] pins to input direction. 2. while key is pressed, mcu will be informed by gpio interrupt then to check kx[4:0] and ky[4:0] status. 3. kx[4:0] keep output data 0, then to r ead ky[4:0] status by register 0x1451[4:0], by reading ky[4:0] status, mcu can know which bit equal 0, allowing it to determine which row is pressed. 4. change pin ky[4:0] from input dire ction to output direction and output dat a 1. change pin kx[4:0] from output direction to input direction then to read kx[4:0] status by register 0x1450[4:0]. by re ading kx[4:0] status, mcu can know which bit equal 1, allowing it to determine which column is pressed. 5. mcu knows which row and column are pressed, so it can determine which key is pressed. pull-l and soft s14 s4 s8 s21 ky[1] s9 kx[1] s2 s22 s24 ky[2] s3 s16 kx[0] s23 s12 s15 s1 ky[3] s5 s11 s17 ky[0] kx[2] s6 s20 s19 s10 s7 s25 s13 kx[4] kx[3] s18 ky[4] figure 4 keypad scanning application circuit 33 rev1.2
w681308 xxxx product description 11. 2 gpio s w681308 has 25 gpio pins that are mainl y used for keypad scan ner, lcm controller, spi, w2s, pcm interface, uart port, for led, cs, sclk, sdi, sdo and csl wi ll act as different functions according to the setting of spi_enb (0x14a0), rdy_enb(0x14ab) and w2s_enb(0x14b0). j tag interface and gpio s. n ote: the pin func d_enb (0x145e), tion lc address name values 0x145e[3] lcd_enb 0 1 1 0 0 0 0x14a0[7] spi_enb 0 0 1 1 1 0 0x14 ab[5] rdy_enb 0 0 0 0 1 0 0x14b0[7] w2s_enb 0 0 0 0 0 1 fu nctions pi n number pin name gpio 0x145e[2:0] for lcd driver spi for lcd driver spi for da isd15000 w2s ta flash co ntrol 11 led gpio 3 gpio 03 gpio 3 gpio 3 spi_rdy gpio 3 13 cs gpio 11 gpio 11 spi_cs spi_cs sp i_cs gpio 11 14 sclk lcd_ckn gpio 10 spi_clk spi_clk spi_clk w2s_scl (0x145e[b1]) 15 sdi gpio 9 gpio 09 gpio 9 spi_sdi spi_sdi gpio 9 16 sdo lcd_tx gpio 8 spi_do spi_sdo spi_sdo w2s_sda (0x145e[b0]) 17 csl lcd_csn gpio 12 pull high gpio 12 gpio 12 gpio 12 (0x145e[b2]) 34 rev1.2
w681308 xxxx product description 11.3 lcd control address access mode value at reset 0x145e r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved r eserved reserved reserved lcd_enb _csn lcd_ckn lcd_tx lcd lcd write out data lcd write out clock lcd rite out chip lect enable (active low) lcd_enb lcd i/o enable control : 1 = enable, 0 = disable set this bit to enable lcd control interface : pin 17 csl = lcd_csn pin 14 sclk = lcd n pin 16 sdo = lcd_tx 1 i/o lcd_tx lcd_ckn lcd_csn w se _ck 1.4 uart control address access mode value at reset 0x14 5f r/w 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 uar enb t io reserved r eserved r eserved re served re served res erved rese rved uart uart ena = enable, 0 = disab io enb i/o ble control, 1 le 35 rev1.2
w681308 xxxx product description 12. pcm interface , ga in stage and mixer 12.1 pcm interface the pcm module is a 16-bit parallel/serial data transfer interfac e. it transfers the 16 bits data from gain-stage/mixer to sing le bit output, and transfers the one bit signal data of input pin to 16 bits data buffer to the gain-stage / mixer. in normal ation, the fs and bclk are gener ated from the analog pll module. pcm interface specific ? ode ? k frequency : 1 m hz. ? ncy selection of the : 8k, 16k and 48k hz. ? lection of the ? pcm fs/dat ? pcm_fs & pcm_bclk inv 12.2 gain stage here are 6 programmable gain stages for transmit and receive path. these gain stages are im plemented to provide a range of +24 db to ?31.5 db with 0.5 db per step. the figure 5 is shown the location of these digi tal gain stages. there are 2 side e before aec block, one after aec block. side tone gain stage is from -0.5db to -31.5db with 0.5db step. figure 5 pcm interface, gain stage and mixer location oper ation: master m only support tx / rx path mute 8 pcm bit cloc 28k, 256k, 512k, 768k, 1m, 1.536m, 2m, 4 3 freque pcm frame sync (fs) 16 bit length se pcm frame sync (fs) : 1~ 16 bits. 4 selection of a location + 1 half bit clock delay. erse mode for i2s interface. ? t tone paths to select from: on 36 rev1.2
w681308 xxxx product description 12. 3 mixer the mixer provides flexible connections among codec blo ck, pcm interface and usb block. we will describe each 2.4 connection case example examples ase connection case of mixer modes and how to configure them below. 1 f igure 6 mixer connection case ca se 0: link codec and usb c 1: link codec and pcm 37 rev1.2
w681308 xxxx product description case 2: link pcm and usb ase 3: link all 2.5 c 1 38 rev1.2
w681308 xxxx product description mixer case examples with r egister setting igure 7 mixer examples with registers setting ase 0: default 0x80 (enable gain stage, link codec_usb) 0x00 (disable pcm) case 1: record conversation register setting: 0x1460 = 0x83 (enable gain stage, link all) 0x1470 = 0x80 (enable pcm) 0x1474 = 0x02 (mute pcm_rx) f c regist er setting: 0x14 60 = 0x1470 = 39 rev1.2
w681308 xxxx product description case 2: record greeting egist 1460 = 0x80 (enable gain stage, link codec_usb) 1470 = 0x80 (enable pcm) 1474 = 0x02 (mute pcm_rx) egister setting: x1460 = 0xf0 (enable gain stage, link codec_usb, record_usb) nable pcm) r er setting: 0x 0x 0x case 3: record me ssage r 0 0x1470 = 0x80 (e 0x1474 = 0x02 (mute pcm_rx) 40 rev1.2
w681308 xxxx product description case 4: play conversation 1 egister setting: nable gain stage, link all) ) 2 x1464 = 0x40 (mute codec a/d in) 0x1467 = 0x40 (mute usb iso out) r 0x1460 = 0x83 (e 0x1470 = 0x80 (enable pcm) 0x1474 = 0x04 (mute pcm_tx case 5: play conversation register setting: 0x1460 = 0x83 (enable gain stage, link all) 0x1470 = 0x80 (enable pcm) 0x1474 = 0x04 (mute pcm_tx) 0 41 rev1.2
w681308 xxxx product description case 6: pro-x fxs : e, link pcm_usb) x1470 = 0x80 (enable pcm) x1465 = 0x40 (mute codec d/a out) 2.6 i2s register setting example he following example will generate i2s interf ace format from the w681308 pcm interface. s for 48khz sampling rate(sr) with 16bits lpcm : 70 = 85 70 [2:0] 70 [4:3] 70 [7] 101 = bclk rate select. sr x 32 bits = 48k x 32 = 1.536mhz ( l, r channels are 16 bits format) 00 = fst location, frame sync is occurred before the msb of the pcm data. 1 = enable pcm interface 72 f0 = for long frame 74 40 = pcm bit clock inverse enable register setting 0x1460 = 0x81 (enable gain stag 0 0 1 t i2 0x14 0x14 0x14 0x14 0x14 0x14 42 rev1.2
w681308 xxxx product description 1 1 3. audio codec interface 3.1 overview he audio codec interface allows the usb audio controller de vice to be connected to one or more of the following: 16 bit internal linear pcm codec and echo cancellation block. 8/16/48 khz codec sampling rate an i2s interface to and from the on chip linear codec. a pcm interface to connect to a ex ternal nuvoton pr ox slic/codec he audio data is flowing between usb interface and codec through 2 segmented fifos that allow mcu processing of udio data. 3.2 audio codec signal path t ? ? ? ? t a 1 figure 8 w681308 codec signal path control transmit path operation the microphone is biased through pins mcp by an internal programmable voltage reference and programmable resistor. the microphone ac signal is gained up by the inpu t amplifier and filtered to prevent aliasing at the input of th e sigma delta adc. the sigma delta adc converts the signal in a 2 bit digital r epresentation, which is decimated and low pass filtered to the base band sampling rate of 8khz to 48khz. a hi gh pass filter can be enabled in the transmit path. 43 rev1.2
w681308 xxxx product description the signal from the digital receive input is filtered through the acoustic echo cancellation filt er and subtracted from the hig h o cancellation is only active in speaker phone operation with 8 khz sampling. the result is rammable time, release ti me and enable signal. the output of the agc can be passed mcu or both (recording a conversation). interface or the usb fifo/mcu. the digital signal can rogrammable digital ga in stage. then, the side tone from the transmit side is added bled when the speakerphone is active. ble enable. the output of the high pass filter goes aker phone speaker driv er, the earphone speaker driver or both. to switch between the earphone driver and the speaker phone driver. at power on pin vref1 is used to control the ramp up of the speaker and earphone driver in order to avoid ?pop? sounds. during operation, the user should lower the volume of the speaker using the software volume ontrol settings, before switching the speaker and earphone driver in order to reduce the ?pop? sounds.; alternatively, a buzzer can be used on the speakerphone driv er outputs, using a 200hz- 32 khz pwm signal. however, the speakerphone can not be used in that case. digital codec the digital codec filter chain is so des igned that it can handle 48k, 16k and 8k rate through its rate change filters. 13.3 microphone interface and auxiliary interface w681308 integrates a fully programmable microphone interfac e. no external components other than the microphone are required to operate the circuit. the microp hone interface can operate in three modes: ? voltage gain mode ? current gain mode ? auxiliary input mode for the current gain mode an internal or external resistor c an be selected to determine the gain. the auxiliary input mode should be used with external resistors. however, an internal gain resistor can be selected. the interface modes above can be selected with register mic_mode [2:0] at address 0x1489. ? voltage gain mode the basic operation is shown below in igure 9 pas s filter output. the acoustic ech with prog then passed to the agc either to the pcm interface, the usb/ receive path operation t he pcm input can be obtained through a multiplexer from the pcm t hen be gained or attenuated through a p t hrough a programmable side tone gain stage. the side tone is disa t he digital signal is then passed through a high pass filter with programma through the interpolation smoothing filter , which produces a 4 bit binary to 15 bit thermometer digital representation for the sigma delta dac. the output of the dac goes through an analog smoothing filter . the output of the sm oothing filter can be ooked up to the spe h a pr ogrammable attenuation switch is used up of the analog section, the slow ramp c f . the microphone is conne nt that the negative terminal of the icrophone is routed separately to the rgnd pin for ?pseudo di fferential? operation, reducing the background noise amplified his can be enforced in the pcb layout by placing a 0 ohm resistor or a ferrite bead. the pin tput of the microphone amplifier and can be used for moni toring the ac level. the voltage gain is et by register mic_gain[7:4] at address 0x1489. this register provides a gain range from 14db to 38db. the gain is set by volt. cted to the pins mcp and rg nd. it is importa m b y the microphone amplifier. t mco is connected to the ou s a ratio of internal resistors, providing accurate gain control. the pin mcp also supplies the bias reference for the microphone . the bias consists of a programmable resi stor and a programmable voltage reference. the programmable resistor is set by register mic_res[7:4] at address 0x1488 and can be set to open and 670 ohm to 10kohm. the programmable voltage reference is set by register mic_bias[2:0] at addr ess 0x1488 and can be set from 1.22volt to 2.74 44 rev1.2
w681308 xxxx product description mic_bias[2:0] 0x1488 electret microphone mic_gain[7:4] 0x1489 + - to adc mic_res[7:4] 0x1488 250 ohm mic_gain[7:4] 0x1489 w681308 voltage gain mode 0x1489 mic_mode=?000? mcp mic_bias[2:0] 0x1488 mco 2 int 1 int '000' mcp adc r r 1 v v += r int1 r int2 rm 0 ohm or ferrite electret microphone mic_gain[7:4] 0x1489 + - to adc mic_res[7:4] 0x1488 250 ohm mic_gain[7:4] 0x1489 w681308 voltage gain mode 0x1489 mic_mode=?000? mcp r int1 r int2 mco rgnd 2 int 1 int '000' mcp adc r r 1 v v += rm 0 ohm or ferrite figure 9 microphone voltage gain mode for higher gain configurations, the current gain mode can be used as in ? current gain mode figu re 10 below. mic_bias[2:0] 0x1488 electret microphone mic_gain[7:4] 0x1489 + - to adc mic_res[7:4] 0x1488 rinternal 0x1489 250 ohm w681308 current gain mode 0x1489 mic_mode=?010?or ?011? mcp mco rgnd r mic_bias[2:0] 0x1488 ext k ? 20 r r i v 250) (r i v ext int ' 010 ' s adc ext ' 011 ' s adc > ?= +?= r int i s i s rm 0 ohm or ferrite electret microphone mic_gain[7:4] 0x1489 + - to adc mic_res[7:4] 0x1488 rinternal 0x1489 250 ohm w681308 current gain mode 0x1489 mic_mode=?010?or ?011? mcp mco r i s i s ext k ? 20 r r i v 250) (r i v ext int ' 010 ' s adc ext ' 011 ' s adc > ?= +?= r int rm 0 ohm or ferrite figure 10 microphone current gain mode 45 rev1.2
w681308 xxxx product description t he current gain mode uses the same programmable microphone bias voltage and resistor as the voltage gain mode. the gain is set by either the internal gain resistor or an extern al resistor, depending on the mic_ mode setting. since the current gain mode is using a single resistor, the gain accuracy is limit ed. however, large gain can be achieved. note that a 250ohm esd protection resistor is connected to the mco pin. this resistor should be considered when calculating the gain. ? auxiliary input mode for non-microphone applications one or more auxiliary inputs can be connected to the mcp pin as shown in figure 11 below. the mic_res register should be set to open in order to disconnect the microphone bias. for the gain setting it is advised to use external gain resistors only fo r optimal matching and accuracy. the 250ohm esd protection resistor should be considered again when ca lculating the gain. note that for this mode the rgnd pin is tied to the external supply ground. a clean ground reference should be used for this. mic_bias[2:0] 0x1488 mic_gain[7:4] 0x1489 + - to adc mic_res[7:4] 0x1488 =?0100? rinternal 0x1489 250 ohm w681308 auxiliary input mode 0x1489 mic_mode[2:0]=?101? mcp mco rgnd rext + vs - rs 1 cs 1 s s ext s ext ' 101 ' s adc r 40 1 c k ? 20 r r 250 r v v ?? = > + ?= rs n cs n mic_bias[2:0] 0x1488 + vs n - mic_gain[7:4] 0x1489 mic_res[7:4] 0x1488 =?0100? + - to adc rinternal 0x1489 250 ohm w681308 auxiliary input mode 0x1489 mic_mode[2:0]=?101? mcp mco rs 1 cs 1 rext + vs - s s ext s ext ' 101 ' s adc r 40 1 c k ? 20 r r 250 r v v ?? = > + ?= rs n cs n + vs n - figure 11 microphone auxiliary input mode 46 rev1.2
w681308 xxxx product description 14. serial peripheral interface 14.1 overview w 681308 built in a serial p terface makes w681308 a eripheral interface (spi) port whic h is a 4-pin (sclk, cs, sdi, sdo) spi interface. this spi n easy to control 4-pin spi device in cluding spi data flash, spi lcm, nuvoton pro-x slic pi module can in codec etc. this device has various clock speed and data forma t by setting relative control registers. the s be operated at clock rates of up to mcu clock rate. figure 12 spi block diagram 14.2 data and signal format of spi there are 5 control bits (csn_add, csn_ more, ck_more, cp and ci) to decide the spi control signal format. register 0x14ab has detail description of the control bits. the packet and page data format is separated to 2 fields: comm and field and the data field. command field (0 ~ 5 bytes) consists of control instruction/code and access address (tx only). data field (0 ~ 256 bytes) consists of write and read data of serial data flash (tx/rx). all command and data bytes are send msb first. command and data field length can be programmed in cmd_len (0x14a1[2:0]) and data_len (0x14a2[7:0]) register fields. it can be bypassed to write control bit cmd_bypass or disable the data_enb. the max command field length is 5 bytes. the max data field ength is 256 bytes in unidirectional mode, and 128 bytes in vided for reference. 4.3 fsm of spi there are 3 states in the spi finite state machine (fsm) module. the initial state is idle when power on. ? idle after enable the spi function (write 0x14a0[7] =1), the fsm start to wait for mcu control (write 0x14a1) to change to next state. if the cmd bypass flag (0x14a1[5]) is tr ue, the fsm will change to data state, then force control logic to shift in/out the data bytes sequentially. if the cmd bypass flag ( 0x14a1[5]) is false, the fsm will change to the cmd state, then force control logic to shift out the command byte s sequentially to external spi device. ? command (cmd) l bidirectiona l mode. thirteen examples are pro 1 47 rev1.2
w681308 xxxx product description after finished shift out the command bytes, the fsm will change to data state if the data_enb ( 0x14a1[4]) is true, or run lse. ta state, the control logic start to shift out write data to ex ternal spi device if spi_rd (0x14a1[3]) is bac k to idle state if the data_enb is fa ? data when fsm goes into da false, or shift in read data from external spi device if spi_rd (0x14a1[3]) is true. in bidirection mode, the control logic wil l ignore spi_rd (0x14a1[3]) and start to shif t in/out the read/write data from/to exte rnal spi device. after finishing shift out/ in the data bytes, the fsm will go back to id le state and wait fo r next transition. idle data cmd 14.4 fifo and ram of spi the spi module takes up to 5 bytes register to write th e control command and takes the 256x8 bytes ram to do the read/write access fifo. in bidirectional mode, the 256x8 by tes ram will separate into two 28x8 bytes sections. one (addr: 0x00~7f) for keep the transmit dat a, and the other one (addr: 0x80~0xff) fo r store the receive data. once the bidirectional mode is enabled, the spi module from addr: 0x80 instead of the addr: 0x00 as in the unidirectional mode. it supports two memory access methods: ? fifo like method x14ac) with hardware control the memo ry read/write address, and increase the read/write pointer automatically after each read/write. the current write and read pointer can be read at register 0x14ae and se tting the read (0x14af)/write (0x14ae) pointer first. hen tx/rx byte counts (0x14ad) = data_len. ? middle flag interrupt ts (0x14ad) = 16 * intr_cnt (0x14a3[7:4]). 1 will automatic put receive data mcu always read/write the same register (0 0x14af. ? direct access method cu can read/write any byte of the memory after m 14.5 interrupt sources the spi module supports two types of interrupt sources: tx/rx finish interrupt ? w when tx/rx byte coun for any other options, refer to the description of the specific registers in w681308 design guide. 48 rev1.2
w681308 xxxx product description 15. nuvoton 2-wire serial bus 1 5. 1 overview nuvoton 2-wire serial bus (w2s) is a simple bi-directional 2-wi re bus for efficient inter-ic control. this design is for w2s master use only, and governed by the mcu. the w2s is us ed to both read/write eeprom and to control various device cluded i2c interface. the w2s controller is equipped wi th 35 bytes fifo in performing formatting and de-formatting. the cu can simply fill up the fifo contents wh ich consists of target device id, high/ low address (depend on the device format); r reading, just set read enable, for writi ng, keep writing data to fifo then set wr ite enable to launch transmission. the w2s controller supports 3 types of page writi ng, 8, 16 and 32 bytes. the w2s controller is designed to support maximum of 32 bytes per page. the fifo depth can support 3 header bytes (one device id, two address) and 32 bytes data. it has various bus speed configurations to support wide range of eeprom bus speed. 16. ice function by jtag std. ieee 1149.1 16.1 overview the w681308 mcu on-chip debugger function fo llows the jtag standard. it provides 8 sets of breakpoints. there is no watchpoint. there are five jtag-style scan chains within t he 8051 and peripheral logic, which enable embedded ice logic. the 5 jtag interface pins tck (jtag test clock input), tm s ag test mode select), tdi (jtag test data input), tdo st (jtag tag controller rese t) are needed to enable the operation. the jtag interface ction pins. w signal on ntrst will reset tap controller or mcu er tap controller reset once. pin description m fo (jt (jta g test data output) and ntr pins are multiplexed with other fun 16.2 scan chains and jtag interface there are five jtag-style scan chains within the tb51 co re and peripheral logic interface. these enable debugging peration and configuration of embedded-ice l ogic. an external pull lo o p ower-on reset will trigg 16.3 table 11 jtag pin description pin name type function tck in jtag test clock with internal pull-up. tms in jtag test-mode select with internal pull-up. t di in jtag test data input with internal pul l-up. tdi is latched on a rising edge of tck. tdo out jtag test data output. data is sh ifted out on tdo at the rising edge of tck. tdo output is a tri-state driver with internal weakly pull-low resister. ntrst in jtag tap controller reset input with internal pull-up. 49 rev1.2
w681308 xxxx product description 16. 4 reset behavior tb51 will start to execute internal code after power on reset. if host jtag ice connects with tb51, the host ice can send command to control the tb51. reset type functional description power on reset 1. reset mcu 2. reset jtag. tap controller will stay in test-logic reset state. 3. execution starts from address 0000 after reset. reset by reset pin or wdt 1. reset chip. reset (including set reset 2. do not reset jtag. tap controll er stays in the original state. 3. if the original tap controller st ate is in run mode, chip reset r state is in halt mode. no any state changed out and reset in sc0) 4. if the original tap controlle ntrs t low 1. no effect on mcu. 2. reset jtag. tap controller will stay in test-logic reset state. 17. ring tone (pwm) generator 17.1 overview t he ring tone or pw here are two tone signals can be mixed to the speakerph nerator with the pwm (pulse width ring tone generator (pwm) specification: m can generate dual frequency tones through on chip speaker driver. t one driver output. this subsection de scribes the ring tone ge modulation) format. ? tone channel number = 2 ? tone volume step = 32 ? tone frequency range = 91hz~23khz 256~1 3216 12 = = nhz n m frequency the y/volu gnal path is shown as figure 13 . figure 13 ring tone generator block tone frequenc me control si 50 rev1.2
w681308 xxxx product description 18. full/half dupl ex acoustic echo cancellation(aec) 18.1 f rol registers f 14 illustrates the block diag the aec unit removes the echo signal caused by the speaker and room reflections. unction cont igure ram of t he full/half acoustics echo cancellation figure 14 signal flow through acoustic echo can cellation in the speech processor 51 rev1.2
w681308 xxxx product description 19. usb device controller and transceiver sb 2.0 fs standard specification and vironment. the usb core embeds one rogrammable 512x8 bit ram to store descriptor. in the setting, the usb core includes five interfaces and 6 endpoints to handle above applications. 19.2 functional description he usb function block diagram is shown below: 19. 1 overview the w681308 includes a full function usb 2.0 full speed contro ller. it supports u tandard usb audio device class and hid device class in microsoft windows en s p t uc sie ucom control endpoint #0 iso-in endpoint #1 iso-out endpoint #2 bulk-in endpoint #3 bulk-out endpoint #4 interrupt-in endpoint #5 iso-sync endpoint #6 tpram 128x16 tpram 128x16 addr_sel reg ctrl pcm tpram 256x8 ctl_out/bulk_out descriptor ram 512x8 tpram 256x8 ctl_in/int_in/bulk_in usb_tst to usb transceiver bist figure 15 usb function block diagram the usb module supports all transfer types (control, bulk in, bulk out, interrupt in, isochronous in, isochronous out and iso-sync) in usb 1.1 spec and w681308 usb embeds 6 endpoi nts include control endpoint 0. the default descriptors are stored in the programmable 512x8 bit ram. the sie module is for handle usb series-interface-engine functions. ucom 52 rev1.2
w681308 xxxx product description mod ule is a bridge to communicate sie and all transf er type modu les. register control module is for handle mcu read/write 308 usb registers. gain stage residing out off usb module is required for adjusts gain of pcm trol application. us b test module connects many internal signals to test pins for help monitor them 0 full speed(fs) 12mbps compliant audio class interface and command support (volume cont rol, mute control, sampling rate selection) support (set/get report) ect 1.5kohm on d+ bus isochronous in/out, bulk in/out, and interrupt in. ? ping-pong fifo control for bulk in/bulk out trans fer to increase data transmission efficiency. ? provide three bytes isochronous sync to synchronize isoc hronous out with pc audio dat a stream and improve voice quality. 19.2.1 endpoints the definitions of em bedded endpoints are: and data signals of w681 data in audio volume con from outside. the features of usb interface are: ? usb specification version 2. ? ? hi d class interface and command ? programmable pull-up resistor to connect/disconn ? support five interfaces and 6 endpoints: control, address type direction maximum packet size (bytes) memory type 0 control in/out 64 64x8 tpram 1 iso in 256 128x16 tpram 2 iso out 256 128x16 tpram 3 bulk in 128 128 x 8 tpram 4 bulk out 128 128 x 8 tpram 5 interrupt in 64 64x8 tpram 6* iso in 3 registers table 12 w681308 usb endpoint definitions note: tpram - dual ports ram 53 rev1.2
w681308 xxxx product description 19.2.2 descriptor ram t he referenced descriptors are stored in the 512x8 bi t ram, programmed by mcu. the address mapping and bank 18-2. definition of this ram are shown in address function size 0 x2000~0x2011 device descriptor 18 byte s c onfiguration descriptor interface descriptor 0x2012~0x217f endpoint descriptor audio class descriptor hid descriptor 366 bytes 0x2140~0x214f string descriptor index 0 16 bytes 0x2 5f 150~0x21 string descriptor index 1 16 bytes 0x2 6f 160~0x21 string de tor index 2 16 scrip bytes 0x217 217f 0~0x string de tor index 3 1 scrip 6 bytes 0x21 f 80~0x21f report descriptor 12 8 bytes table 13 usb descriptor ram definitions 54 rev1.2
w681308 xxxx product description 20. 20.1 absolute maximum ratings elect rical characteristics condit ion value unit junction temperature 150 0 c storage temperature range -65 to +150 0 c lead temperature (soldering ? 10 300 0 c seconds) lqfp-48 nce, ty 76 thermal resista pical c/w voltage applied to any pin (v ss - 0.3 ) to (v dd + 0.3 ) v input cu y digita +/- 10 ma rrent applied to an l input pin esd (hu 2000 v man body model) v dd - v ss -0.5 to +3.63 v v ddl - v ss -0.5 to + 1.98 v power d 0.5 att issipation w n m ote: stresses above the value listed m exposure to absolute maximum ratings ay affect device reliability. functional operation is not implied at these conditions. 20.2 recommended operating conditions ay cause permanent damage to the device. condition value unit commercial operating temperature 0 to +70 0 c industrial operating temperature -40 to +85 0 c supply voltage (v dd ) using external regulator +3.13 to +3.47 v supply voltage (v ddusb ) using intern al regulator and external transistors +4.4 to + 5.25 v ground voltage (v ss ) 0 v 55 rev1.2
w681308 xxxx product description 20. 3 dc characteristics symbol parameter min typ max unit vil input low voltage -0 0.8 v .3 vih in 2 3.6 v put high voltage vt t 1 1 1.49 v hreshold point .32 1.4 vt+ s 1.49 1.54 1.58 v chmitt trigger. low to high threshold point vt- schmitt trigger. high to low threshold point 1.24 1.29 1.34 v ii input leakage current @ vi =3.3v or 0v 10 a ioz t nt @ vo =3.3v or 0v 10 a ri-state output leakage curre rpu p 38 54 83 k ull-up resistor rpd p 25 49 110 k ull-down resistor vol o oltage @ iol (min) 0.4 v utput low v voh output high voltage @ ioh (min) 2.4 low level output current @ vol =0.4v 2 ma 2.2 3.7 5.3 ma iol l ent @ vol =0.4v 16 ma 19.6 29.8 39.0 ma ow level output curr high level output current @ voh =2.4v 2 ma 3.2 6.4 10.6 ma ioh high level output current @ voh =2.4v 16 ma 23.1 46.8 77.8 ma 20.4 analog transmission characteristics avdd=3.13v ? 3.47v; v ss =0v; t 5 c; all adc tests using auxilia ode @ 0db g a =-40 c to +8 ry input m ain tr (adc) ansmit receive (dac) symbol condition parameter typ min max min unit max full scale level adc (single ended) 1.218 2.436 --- --- - --- --- --- --- v pk v pk t xmax dac (differential) --- -- absolute gain 5 c; 0 .40 -0.40 +0.40 db g abs -3dbfs @ 1020 hz, avdd =3.3v; t a =+2 -0.40 +0 absolute gain variation with te g abst to t a =+70 c t a =-40 c to t a =+85 c -3dbfs 0 -0.10 -0.20 +0.10 +0.20 -0.10 -0.20 +0.10 +0.20 db t a =0 c mperature absolute gain variation with supply voltage g abss avdd=3.13v ? 3.47v; - 3dbfs @ 1020 hz; t a =+25 c 0 -0.10 +0.10 -0.10 +0.10 db 56 rev1.2
w681308 xxxx product description 20.5 analog distortion an d n oise parameters all adc tests using auxiliary input mod in 20. av .13v a =-40 c to +85 c; 8khz sampling e @ 0db ga 5.1 8khz sampling dd=3 ? 3.47v; v ss =0v; t transmit (adc ) rece ive ( c) da er symbol condition paramet min typ m ax min typ unit max signal to noise ratio 80 94 80 88 -- db snr idle channel a-weighted -- total harmonic di -- -77 -67 -- -77 -67 db stortion thd3 -3dbfs @ 1020 hz, 32ohm speaker load total harmonic distortion -3dbfs @ 1020 hz, 8ohm speaker load -- -77 -67 -- -70 -60 db thd8 total harmonic di s @ 1020 hz, er load -- -79 -69 -- -65 -55 db stortion thd4 -6dbf 4ohm speak frequenc pons w pass cut-off 3.36 khz y res e frl -3db lo 3.36 power supply rej dc 70 88 70 85 --- db ection psrr a to 3.4 khz a-weighted v ddusb ; 35mvrms --- 20. hz sampling 5.2 16khz sampling avdd =3.13v ? 3.47v; v ss =0v; t a =-40 c to +85 c; 16k transmit (adc) receive (dac) parameter symbol condition min typ max min typ unit max signal to noise r ati snr 6 o idle channel a-weighted 80 93 -- 80 8 -- db total harmonic d istort t 020 hz, aker load - -66 -- 78 8 ion hd3 -3dbfs @ 1 e 32ohm sp -- 76 - -6 db total harmonic distortion t , -6 -- 0 hd8 -3dbfs @ 1020 hz 8ohm speaker load -- -76 6 -7 -60 db total harmonic distortion t 0 hz, load -- -79 -69 -- db hd4 -6dbfs @ 102 4ohm speak er -65 -55 f ponse -3db low pass cut-off 6.73 6.73 khz requency res frl power supply re jectio p s hz weighted n srr a v ddusb ; 35mvrm dc to 6.8 k a- 70 89 --- 70 85 --- db 57 rev1.2
w681308 xxxx product description 20.5 .3 48khz sampling avdd=3.13v ? 3.47v; v =0v; t =-40 c to +85 c; 48k ss a hz sampling transmit (adc) receive (dac) parameter symbol condition min typ max min typ unit max signal to noise ratio snr idle channel weig 80 80 db a- hted 92 -- 85 -- total harmonic thd3 -3dbfs @ 1020 hz, 32 -- -77 -67 -- -76 -66 db distortion ohm speaker load total harmonic thd8 -3dbf 0 hz, 8o -- -77 -67 -- -69 -59 db distortion s @ 102 hm speaker load total harmonic thd4 -6dbf 4o -- -78 -68 -- -65 -55 db distortion s @ 1020 hz, hm speaker load frequency response frl -3db 20.2 20.2 khz low pass cut-off power supply psr v d a- 70 88 --- 66 76 --- db rejection r a ddusb ; 35mvrms c to 6.8 khz weighted 20.6 programm able o t a =-4 omponents per application diagram; utput line ar regulator 0 c to +85 c; using discrete c min (2) typ (1) max (2) parameter symbol condition unit recommended usb supply voltage v ddusb low power mode (100ma) high power mode (500ma 4.4 5 5.25 v v ) 4.75 5 5.25 regulated supply voltage v dd no load, normal o pera 3 3.47 v tion 3.1 3.3 total suspend mode current i sp mode pull-up and discrete -- 463 -- ua suspend including usb regulator operating supply current i vdd on -- 38 -- ma no load, normal operati voltage drop v drop0.5 500ma -- 0.006 -- v v ddusb =5v, load= voltage drop v drop1 v ddusb =5v, load=1a -- 0.06 -- v note 1: typical values: ta = 25c limit ara ton via elect testing or char erizat not a ecific ns ar 100 percent tested note 2: all min/max s are gu nteed by nuvo rical act ion. ll sp atio e 58 rev1.2
w681308 xxxx product description 20.7 eristics ( 25c, dvdd= 3.3v, vddl =1.8v) usb p hy electronic charact parameter symbol condi tion min. typ. max. unit d e for u stage 3. v c supply voltag sb output vdd_usb 3.1 3 3.5 input voltage range for usb_dp/dn usb_dp _dn 0 3.5 v usb input high v 2.0 v ih input lo w v v il 0.8 differential inp ut sensitivit 0.2 v y v di differential co mmon-mode e 0.8 v rang v cm --- 2.5 single-end receiver threshold v se 0.8 2.0 v output low v ol v 0.3 output high v oh 2.8 v output signal cross voltage v crv 1.3 2.0 v pull -up resistor r up 1.3 1.61 1.9 k ? d river output resistance z drv 8 19 ? tran ance c in 20 pf sceiver capacit driver rise time t r 4 8 20 ns driver fall time t f c edge =30 c = 50 l rs=25 o pf hms pf 4 8 20 ns rise and fall time matching lrlf = t lr/ t lf 90 100 110 % t lrlf t standby 100 na input mode 2 ma vdd_usb supply current gh resistor) i output mode 2 ma * (exclude internal pull hi usb 59 rev1.2
w681308 xxxx product description 20.8 usb pll electronic characteristics parameter symbol condition s min. typ. max. unit operation voltage v pll 3 3.1 3.3 3.47 v input clock frequency range f in 12 mhz pll output frequency mhz f out 48 vco frequ ency o mhz f vc --- 48 --- ouput duty cycle 6 66 46 5 % pll short-term peak to peak outp ut jitter ter ps t jit 7 pll lock in time t re ady us 25 60 rev1.2
w681308 xxxx product description 61 rev1.2 21. typical application reference circuit figure 16 w681308 reference design application circuit 21.1 usb voip speaker phone application the application diagram illustrated that the w681308 is a soc with very low bom system design. externally it supports a variety interfaces such as keypad, lcm, slic, spi flash/eeprom, microphone and speakers directly. external 12m crystal as well as a 5v to 3.3v linear regulat or is required. ring tone download and play back is through the same audio dac path with a switch for ringing and speech. s20 /csl c16 100nf dgnd s15 pcmr r6 2k w681308_lqfp u1 13 14 17 15 18 19 20 16 21 24 25 27 28 29 30 31 32 33 35 36 26 34 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 22 23 /cs sclk /csl sdi fs bclk pcmr sdo pcmt vpp agnd earn avdd earp spp agnd rgnd mco vref2 vref1 spn mcp regl ky4 ky3 ky2 ky1 ky0 kx4 kx3 kx2 kx1 kx0 jtag rtt rtr dgnd xtalo xtali vddl dvdd dn dp dgnd gpio3 gpio0 gpio1 gpio2 ua ua c10 100nf ky3 up1 earp s6 uartt gpio2 kx0 vdd_3.3v dn hangup c8 10nf pcmt dp c17 100nf dgnd ky2 user dgnd agnd 5 vdd_3.3v tp1 1 up q1 mmbt3906 1 2 3 agnd s19 7 xtalo /cs 2 c14 30pf ky4 bclk rec1 receiver 9 r11 100 agnd s4 vref2 s14 dgnd gpio3 s11 # agnd dgnd s2 s16 pushbutton dial c15 30pf c6 100nf c12 51pf s9 usb_5v c3 220uf/10v r12 100 s8 dgnd spp xtali left gpio1 kx1 s23 dgnd r5 100k spn s1 s21 pcm interface is for external audio device or usb ata wtih pro-x skype q2 pzt2222a s17 pushbutton sdi usb_5v agnd sclk vdd_3.3v kx2 c9 100nf uartt c2 10nf r9 25 spk1 speaker 1 dgnd s3 c4 33pf vdd_3.3v 6 kx4 mco c5 100nf melody dgnd pcmt dgnd dgnd agnd lcd module (serial interface) sclk sdo /csl rs reset vdd gnd s25 dy1 12m 4 dgnd ky0 s10 0 r10 25 ky1 s22 d1 led pcmr agnd agnd rgnd fs q3 mmbt3904 s13 3 down1 c7 33pf bclk vdd_3.3v uartr dgnd dgnd vref1 /cs 8 mcp sdi the shielding of the usb connector can't connect to any gnd. uartr mode mute + c1 1uf/10v r3 60k mic1 micropho ne 1 2 r1 1m s12 vdd_3.3v sdo djp1 usb connector 1 2 4 3 vcc d- gnd d+ shielding agnd s24 s7 r2 100k r7 270 s5 dgnd * dgnd down vdd_3.3v gpio0 c11 10nf fs kx3 r4 300k earn d2 led right r8 1m regl s18 c13 51pf
w681308 xxxx product description 2 2. package dimensions 681308dg is in 48 pin low-profile quad flat package (lqfp). w in inch in mm symbol min nom max min nom max a - -0.063 - - 1.60 a1 0.002 0.004 0. 006 0.05 0.10 0.15 a2 0.053 0.055 0. 057 1.35 1.40 1.45 b 0.005 0.008 0.010 0.15 0.20 0.20 c 0.004 0.005 0.008 0.10 0.15 0.20 d 0.272 0.276 0.280 6.90 7.00 7.10 e 0.272 0.276 0.280 6.90 7.00 7.10 e 0.014 0.020 0.025 0.35 0.50 0.65 h 0.350 0.354 0.358 8.90 9.00 9.10 d h e 0.350 0.354 0.358 8.90 9.00 9.10 l 0.018 0.024 0.030 0.45 0.60 0.75 l 1 - 0.039 - - 1.00 y - - 0.004 - - 0.10 0? - 7? 0? - 7? 62 rev1.2
w681308 xxxx product description 23. ordering information nuvoton part number description when ordering w681308series devices, please refer to the following part numbers: w681308_ _ part number temp range ( o c) package package material W681308DG -40 to 85 48-lqfp pb-free package material: g = pb-free package product family package type: d = 48-lead quad flat pack package (lqfp) 63 rev1.2
w681308 xxxx product description 24. revision history version date page description v0 9 preliminary version july, 2007 v1.0 august, 2007 update electrical characteristics v1.1 2008 ke r / earphone attenuation s wi tch march, upd ate spe a v1.2 march 200 9 fo rmat of the datasheet chan ged ate logo up d important notice ted for use as compone nts in ystems or equipment intended for su rgical implantation, atom ic energy control inst ruments, airpl ane or spaceship instrume nts, transpor mbustion control instrument s, or for oth er a int su r s i fe. furthermore, nuvo ton products ar e not intende d fo s w lur t o t s could result or le ad to a situat ion w herein pers onal injur t i ronmental damage could occur. uvo ton cust omers us ing or selling these pr oducts for use in such applic ations do so at their ow n risk nd agree to fully indemnify nuvo ton for any damages resulti ng from such improper use or sales. uvo ton products are not designed, intended, authorized or wa rran n s tation instruments, tra pplicatio ns ffic signal instruments, co ppor t o end ed to ust ain l r applica ti on y, death or sev he rein fai ere proper e of nuv o y or env n prod uc n a 64 rev1.2

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